Very-large-scale integration (“VLSI”) circuits and other integrated circuits are made up of interconnected cells that include a group of transistors and interconnect structures. Each cell must be powered from a power supply through a power grid. The power grid of the circuit refers to the wires or buses used to supply current to the logic devices of each cell and to ground buses used to take current away. As electronic circuit densities increase and technology advances, for example, in deep-sub-micron circuits, skilled designers attempt to maximize the utilization of the design layout and the manufacturability and reliability of the circuit, as well as optimizing power consumption.
Specifically, due to the more restrictive temperature constraints and increasing requirements of the battery life, power has become a very important optimization objective for modern VLSI designs. An effective way to reduce power consumption is to put more emphasis on the design and optimization of clock networks, since among the overall chip power consumption, more than 40% of the power can be consumed by the switching power of the clock network.
One reason that clock network consumes so much power is because the clock signals switch much more frequently than regular signals. Another reason is that the clock network often drives a large number of flip-flops which create a large amount of load capacitance. Power optimization for clock networks has been studied for decades and many techniques, such as clock gating, clock buffer sizing, dynamic voltage/frequency scaling, etc., have been developed. However, due to the more and more critical design requirements, simply optimizing the clock routing and optimal buffer sizing is not sufficient enough to satisfy the design requirements.